Hermetically encapsulated component and waferscale method for the production thereof

ABSTRACT

A component having a sandwich-like structure is described, in which the chip that carriers the component structures is glued together with a frame structure and a diffusion-proof cover, in such a manner that the component structures are disposed in the interior of the structure and preferably in a cavity. The layer transitions of the structures are protected, at the side edges, with a metallization. Interfacial connections through the cover connect contacts on the underside of the cover with the connector metallizations of the component structures on the chip. The interfacial connections are sealed with an underside metallization.

The invention relates to a component having microelectronic componentsincluding MEMS and MEOMS—microelectronic/(optical)/mechanicalsystems—having a hermetic encapsulation and a wafer level packaging forthis component, in which an optimal hermetic seal in the sense of amoisture diffusion seal is produced.

For almost four decades, the integration density in microelectronics hasbeen following “Moore's Law,” which states a doubling approximatelyevery 18 months, with simultaneous halving of the production costs.Traditionally, the production of microelectronic products has beendivided into the so-called front end (essentially application andstructuring of thin films on wafers) and, after these are sawed intoindividual chips, the so-called back end (assembly of the chips oncarriers, electrical contacting, and enclosure or enveloping).

The mechanical and electrical connections of the chip to the carrier arebrought together into a single step with the flip-chip technique. Inthis way, significant miniaturization and better signal transmission dueto low inductance values is made possible by means of this connectiontechnique.

The combination of flip-chip assembly with a utilization technique inwhich a plurality of chips is mounted on a common carrier isparticularly advantageous. In this manner, components are now beingimplemented whose footprint does not exceed the actual chip arearequired for active structures and connections by more than 20%, withthe term chip sized package (CSP) being commonly used for this.

Lateral chip dimensions of approximately 1 mm are quite below suchdimensions where conventional housings (“tub” with lid) could be used.For these reasons, all the leading semiconductor manufacturers havedeveloped packaging concepts, in recent years, which provide for theencapsulation process completely on the wafer level, i.e., beforeindividualization of the components, after wafer structuring.

A true wafer level packaging avoids the individual handling ofindividual chips. With this, the implementation of a true CSP is madepossible even with very small chip dimensions. Fundamentally, all thehousing functionalities can be implemented on the wafer level. Asidefrom the protection against mechanical and climatic influences, as wellas the provision of electrical connections that are compatible withindustry standards such as surface assembly and re-flow solders,re-wiring can also take place here, for example. In this connection,chip connectors can be freely positioned on the outside housing surface.This is made possible by means of one or more insulation layers,interfacial connections, and conductive structures. Internal connectionsare also possible in this manner.

The demand for true CSP is further emphasized by the pressure towardsminiaturization and, to a particular degree, in the case of expensivesubstrates (e.g., LiTaO₃, GaAs).

For semiconductor components that do not require any housing cavity, onthe basis of their method of functioning, there are a large number ofappropriate concepts. Some of them have already become so broadlyestablished that they are offered on the packaging of specializedservice providers. An example is the method known under the trademarkUltraCSP.

A fundamental technical problem of all solutions paths that have beenproposed until now is the long-term reliability of the components, sincethe internal and external connections become fatigued due to temperaturechange stress. This must particularly be taken into account by means ofcoordinating the thermal expansion properties of the materials used.

The stated task is made even more difficult as soon as the demand for ahousing cavity for the component structures is added, for example in thecase of SAW (surface acoustic wave) components. Often, a hermetic sealin the sense of a diffusion seal of this cavity is also demanded, sinceotherwise the resistance to damp heat can be insufficient, resulting incorrosion, problems caused by condensate on active structures, problemswith the moisture content of polymers used in soldering processes,etc.). A hermetic seal can fundamentally not be achieved withpolymer-based molding masses, resins, or adhesives, since thesematerials are more or less permeable for gases and moisture, due topermeation processes.

In WO2000/3508A1, an active structure on a wafer is surrounded with aframe of photoresist, for example, onto which a circuit board is gluedas a cover. Interfacial connections guide the electrical connectors fromthe chip to contacts on the circuit board. No sufficient hermetic sealis achieved with the sealing layer that covers the back of the chip aswell as the side surfaces of the component, since the circuit board isnot completely covered, because the usual resin laminates with fiberreinforcement recommended as the sealing layer are particularlydisadvantageous in terms of their diffusion seal, since moisture canspread along the border layer between the polymer and the fibers.However, the decisive disadvantage is that the sealing layer describedcan no longer be applied on the wafer level, but only afterwards, on theindividual component.

From WO2001/4318A1, another method for packaging is known. Here, thewafer is glued between two covers. Frame-shaped spacers define a cavityabove the active chip structure, if necessary. The electrical contactsrun around the chip to contacts (110) on the back cover, by means ofmetal structures that were originally produced on the wafer and thosethat are structured in sawed notches along the separation lines (108).The joining materials are polymers, with which no diffusion seal can beachieved, as was explained. The concept does not permit completemetallization (and therefore a seal), since the electrical connectionsrequire several metal structures that are electrically separated fromone another.

It is therefore the task of the present invention to indicate a simpleand cost-effective method for true CSP, on the wafer level, for SAWfilters and other components, with which method components having adiffusion seal can be produced.

This task is accomplished, in the present invention, with a component asrecited in claim 1. A method for the production of the component, aswell as advantageous embodiments of the invention, can be derived fromadditional claims.

The component according to the invention fulfills all of theserequirements and is furthermore compatible with various technologiessuch as SAW and FBAR (=thin film bulk acoustic wave resonator).Furthermore, numerous applications are possible in microsystemtechnology, which is diversifying, and in integrated optics and sensorsystems.

The invention indicates a component having a hermetic encapsulation,which has a sandwich-like glued structure. The structure comprises achip, preferably made of a piezoelectric material, on the surface ofwhich component structures and connection metallizations connected withthem are implemented, a frame structure that surrounds the componentstructures in ring shape, as well as a diffusion-proof cover that formsa cavity for the component structures, resting on the frame structureand being rigidly connected with it. Furthermore, the component has aback face metallization that is applied to the back face of the chip andcovers at least all of the surfaces of the sandwich-like structure thatface towards the outside, at the edges of the component. This means thatall of the layer transitions of the sandwich-like structure are coveredwith the back face metallization at their butt edges (outside edges ofthe component). The cover has contacts on the surface that areconnected, in electrically conductive manner, with the componentstructures on the chip, using interfacial connections through the cover.The interfacial connections are guided through holes or recesses in thecover that are completely metallized on the inside surfaces, with anunderside metallization, and thereby are sealed with a diffusion seal.

The component according to the invention has an improved hermeticencapsulation, since all of the potential leakage points of thecomponent are provided with a sealed metallization. The metallizationcan be applied to the back face of the chip, over its entire area, andgoes down past the butt edges of the border areas. The interfacialconnections, which provide access to the interior of the encapsulation,are also securely sealed with an underside metallization. At the sametime, it is ensured that the component requires only an insignificantlygreater footprint than a naked chip (bare die), and therefore issuitable for the production of further miniaturized components. Thestructure that is actually already known, forming a closed cavity forthe component structures, also allows a secure and contact-freeencapsulation even of sensitive component structures. Such sensitivecomponent structures are particularly known in the case of componentsthat work with acoustic waves, such as SAW components, FBAR resonators,as well as in the case of numerous components of microtechnology, aswell as in the case of integrated optical and opto-electronicapplications, or in sensor systems.

In an advantageous embodiment of the invention, the frame structuresurrounds the components structures in ring shape, for one thing, and,furthermore, forms branches or insulated islands that face inward, whichsurround another cavity within the sandwich-like structure, in which theconnector metallizations lie exposed on the surface of the chip. In thismanner, it is possible to guide the interfacial connections through thecover, into these additional cavities, without the cavity with thecomponent structures being opened. This also makes it possible to keepthe component structures free of metallization during the production ofthe underside metallization, without additional efforts being requiredfor this purpose, for seals or covers.

In another embodiment of the invention, another wiring level is providedwithin the sandwich-like structure, which is connected both with theconnector metallization on the chip and with the contacts on theunderside of the cover, by way of interfacial connections. In a simpleembodiment, the wiring level can be applied on the frame structure.However, since, in the case of a miniaturized component, littleadditional space for the wiring level is available above the framestructure, this wiring level cannot be used for the production ofcomplex circuitry, but it can be used to produce track crossings withoutany short circuit.

It is advantageous that in another embodiment of the invention, at leastone intermediate layer is inserted between the frame structure and thecover as a wiring level, on which sufficient space is available for thewiring level, on its top or bottom. Then it is also possible to producemetal structures in the wiring level, with which both tracks andconcrete passive component structures are implemented, which are wiredto the component structures. Capacitors, inductors, and ohmic resistorsare particular possibilities as concrete components.

The intermediate layer is preferably but not necessarily made of thesame material as the frame structure. This guarantees a simple andreliable connection. Preferred materials for the frame structure and, ifapplicable, intermediate layers are a benzocyclobutene, a polyimide, ora benzoxazol. These materials have proven themselves to be particularlyadvantageous with regard to temperature stability, adhesion to ceramicand metallic layers, with regard to metallizability and structurability.These polymers are also available or can be produced in photo-sensitizedversions, which can be structured by means of direct exposure. However,polyurethane (PU), epoxy resin, and acrylates are also suitable as theintermediate layer and frame structure.

The most important requirement for the diffusion-proof cover is itsdiffusion-proof structure. Furthermore, it is advantageous if thematerial has sufficient rigidity and mechanical strength. Therefore,ceramic, metal, and, in particular, glass are preferred as a materialfor the cover.

Since the at least one additional wiring level is preferably applied toa frame structure and/or to additional (organic) intermediate layers,the cover is preferably in one piece or in one layer. Fundamentally, itis also possible, in this way, to use a multi-layer cover, if theadditional layers or their connections can be configured to besufficiently diffusion-resistant. It is also possible to dispose awiring level on the top of the cover, but in the component, this hardlydifferentiates the cover from a wiring level that is arranged on theintermediate layer.

In an advantageous embodiment, the cavity that surrounds the componentstructures is filled with a gas, e.g., a protective gas, in order toachieve specific break-through characteristics in case of over-voltage,which gas can raise or lower the break-through voltage. It is alsopossible to establish a dew point in this manner.

For the production and for the achievable seal, it is advantageous ifthe interfacial connections have a conical cross-section that narrowsnoticeably towards the interior, into the structure. It is alsoadvantageous if the outside edges of the structure are slanted, so that,starting from the back face of the chip, by way of the frame structure,to the carrier, an increasing cross-section is obtained. A conicalformation of the interfacial connections and slanted side edgesfacilitate the production of a sealed metallization, and thereby alsoimprove the hermetic seal of the component interior. If the interfacialconnections pass through additional layers, in addition to the cover,the openings for the interfacial connections are preferably disposedconcentrically and are configured to be conical in all the layers.

In this connection, a component can comprise one or more individualfunctional units (in the case of SAW components, for example, “2 in 1”or “n in 1” filters), or can be structured in multi-layer technology ormixed technology. Such components, which can be configured on a commonchip, can be integrated in simple manner. It is also possible that thecomponent comprises hybrid structures, in which micromechanical,optical, and microelectronic or passive electronic components, forexample, are integrated to form a component, or to form a componentaccording to the invention.

In the following, the invention and, in particular, the method for theproduction of a component according to the invention, will be explainedin greater detail, using exemplary embodiments and the related figures.The figures are only schematic, they are not true to scale, and they donot reproduce the correct size relationships.

FIG. 1 shows a component according to the invention, in schematiccross-section,

FIG. 2 shows a schematic top view of the chip front face,

FIG. 3 shows a cross-section through another component having anintermediate layer,

FIG. 4 shows another schematic top view of a chip front face,

FIG. 5 shows a wafer with a frame structure applied to it, in a topview,

FIG. 6 shows a sandwich-like structure consisting of a wafer, a framestructure, and a cover,

FIG. 7 shows the structure after the production of wedge-shaped cutsinto the chip,

FIG. 8 shows the structure after the production of the back face andunderside metallization,

FIG. 9 shows several types of possible interfacial connections, using aschematic cross-section.

FIG. 1 shows a component according to the invention, in schematiccross-section. The component has a sandwich-like structure, in which achip CH provided on its front face with component structures BS, and acover AD are glued together, a frame structure RS acting as a spacer.The component structures BS are disposed in a cavity between cover ADand chip CH. The side edges of the component are slanted on the chipside, and are provided with a back face metallization RM. Here, thiscovers the entire back face of the chip, and reaches as far as theregion of the side edges of the cover AD, which is also slanted, so thatall of the butt edges SK that form the border areas between chip, framestructure, and cover at the chip side edges are covered by the back facemetallization RM. At least one interfacial connection is guided throughthe cover, and provided on the inside surfaces with an undersidemetallization UM. This connects a connector metallization AM on the chipwith an underside contact UK on the underside of the cover AD. Theconnector metallization AM is connected with the component structuresBS, in electrically conductive manner. All of the surfaces of thecomponent therefore either consist of cover AD, which consists of adiffusion-proof material, or are covered with a metallization, which isalso extremely sealed against diffusion. This has the result that thecavity in which the component structures are disposed is hermeticallysealed against the outside world.

The chip comprises, for example, of a semiconductor material such as Si,SiGe, or a III/V connection semiconductor such as GaAs, InP, InSb, etc.

Piezoelectric materials such as quartz (SiO₂), lithium niobate (LiNbO₃),lithium tantalate (LiTaO₃), lithium tetraborate (Li₂B₄O₇) langasite(La₃Ga₅SiO₁₄), berlinite (AlPO₄), gallium orthophosphate (GaPO₄), zincoxide (ZnO), gallium arsenide (GaAs), etc., or layers thereof onsubstrate wafers, are also suitable as base materials for the chip.

The component structures BS can be configured as electrical conductors,micromechanical or micro-optic structures, or as sensors.

FIG. 2 shows the arrangement of the frame structure RS, in a schematictop view of the front face of the chip CH. The structure is closed in aring shape in the outside region of the chip surface. In the embodimentshown here, the frame structure has a branch AL, which is also closed inring shape, which surrounds another, smaller region within the framestructure. This is the region also shown in FIG. 1, in which theinterfacial connection is provided, so that there, the undersidemetallization UM can enter into contact with the connectormetallization, which in turn is connected with the component structuresBS in electrically conductive manner.

FIG. 3 shows another embodiment of a component according to theinvention, in which an intermediate layer between frame structure andcover AD is disposed in addition to the frame structure in FIG. 1. Inthe case shown, the cavity for the component structures is createdbetween intermediate layer ZS and chip CH. In this connection, the framestructure RS serves as a spacer. Another wiring level VE is providedbetween the intermediate layer ZS and the cover AD, in which electricalconnections or concrete passive components can be disposed. The wiringlevel VE is connected with the connector metallization AM on the surfaceof the chip CH by way of an interfacial connection DK₁. The wiring levelVE is connected with the underside contact UK on the underside of thecover AD by way of the underside metallization UM of another interfacialconnection DK₂.

This embodiment has the advantage that parallel to the surface that isprovided for the component structures BS, a different level is utilizedfor wiring, i.e., switching. This allows a further reduction in thefootprint required for the component. The interfacial connection DK₂from the underside of the cover AD to the wiring level VE can be carriedout more simply and more non-critically with regard to adjustment thanan interfacial connection that leads from the underside to the chipfront face, such as that shown in FIG. 1, for example. This facilitatesproduction.

For efficient production of components according to the invention, workstarts on the wafer level. FIG. 5 shows details of the surface of awafer W already provided with component structures (not shown in thefigure), onto which a frame structure RS is applied. The frame structureRS is structured in such a manner that the component structures that areprovided for an individual component are surrounded in ring shape by thepartial structure of the frame structure. The later division intoindividual components subsequently takes place along separation linesTL, of which, for reasons of clarity, only two are shown in the figure.The separation lines run along structures of the frame structure,specifically in such a manner that during division into individualcomponents, frame structures closed in ring shape remain on eachindividual component. The frame structure is preferably applied to thefront face of the wafer, or alternatively, on the top of the cover. Theframe structure can be applied to the entire area at first, and can thenbe structured. An appropriate film can be laminated on when applying thelayer over the entire area. It is also possible to spin on or print on alayer over the entire area. It is also possible to apply the framestructure in structured manner, for example by laminating on astructured film, or by printing it on. It is also possible to apply aroughly structured layer for the frame structure RS at first, and tomicrostructure it later.

For structuring, it is possible to adjust the material for the framestructure RS to be photosensitive, to expose it by way of a mask orscanning, and subsequently to develop it. It is also possible tolaminate on a dry resist film, to expose it, and subsequently to developit. It is also possible to structure a layer that cannot bephoto-structured, using a resist mask, and subsequent wet chemicaletching or plasma etching. Another possibility is to microstructure alayer for the frame structure, which has been applied over the wholearea, or has been roughly pre-structured, by means of microablation.

Not shown in FIG. 5 are branches of the frame structure or islands,which surround the regions of the surface of the wafer in ring shape, asshown in FIG. 2 for the individual component, in which the contacts tothe contact metallization AM are provided.

FIG. 4 shows such an island-shaped additional frame structure RS_(i),which is produced together with the frame structure RS. The componentstructures BS are indicated schematically in the figure, by means of thearea that can be occupied by the component structures. Within theisland-shaped frame structure RS, an interfacial connection can createcontact to the connector metallization on the surface of the chip orwafer.

After the frame structure has been produced either on the wafer W or onthe cover AD, in structured manner, the sandwich-like structure can beproduced by means of gluing, for example in that the cover AD is gluedtogether with the frame structure that has already been produced on thechip front face, or the chip or wafer is glued to the frame structure RSthat has been applied to the cover. The height of the frame structure isadjusted in such a manner that it is clearly higher than the height ofthe component structures. In this manner, it is guaranteed that thecomponent structures BS are disposed in the cavity surrounded by theframe structure, at a distance from the cover AD.

FIG. 6 shows the arrangement after gluing, in details, using a schematiccross-section that comprises two individual components.

If, as was already explained using FIG. 3, an intermediate layer ZS issupposed to be produced to accommodate an additional wiring level VE,this can fundamentally be achieved using a method called PROTEC, as itis described in EP0759231B1, for example; reference is hereby made toits complete content.

In DE 100 064 46 A1, another solution that can be used according to theinvention is proposed. It comprises laminating a very thin ancillaryfilm onto a frame structure, over a cavity, applying a reaction resinthat can be processed in liquid form, and structuring the resin layerand the ancillary film, wherein the removal of the ancillary film, whichis exposed above contact holes, for example, can take place by means ofsolvents or plasma.

According to the invention, it is furthermore proposed to apply apolymer that can be photo-structured onto an ancillary film. For thispurpose, the ancillary film can be clamped into a device. Suitable filmsare available in good mechanical and optical grades, in thicknesses tobelow 1 μm (e.g., capacitor films). The layer, which is viscous atfirst, can be adjusted in a broad range between gel-like andsolid/tacky, by means of heat processes. In this state, the layer,together with the ancillary film, can be laminated onto the framestructure and can be photo-structured through the ancillary film, whichis then transparent. The ancillary film is then completely removed insimple manner, for example during the subsequent development process.The structured and cured polymer remains, which can now form theintermediate layer and thereby can offer an additional area for theproduction of a wiring level.

Alternatively, the intermediate layer can also be implemented by meansof gluing a film, a polymer film, or a thin glass layer onto the firstlayer, over the entire area, and subsequent photo-structuring.

Contact areas, for example in the form of solder pads or bumps, can beapplied directly to the covering.

The additional wiring level VE can also be applied on the surface of theframe structure RS that faces the cover. For this purpose, the framestructure is first produced on the wafer W and structured. Subsequently,the component structures are covered with a protective cover, forexample with a protective varnish. Subsequently, the metallization forthe wiring level is produced, for example by means of metallization overthe entire area, and subsequent structuring of the latter. In the nextstep, the protective varnish is removed. An interfacial connection fromthe underside of the cover to the wiring level on the frame structurethen no longer has to be guided to the surface of the wafer. This againsaves area space and allows a more precise adjustment of the interfacialconnection.

The cover is now glued onto the intermediate layer that has beenprepared in this manner, or onto the frame structure, as in FIG. 6. Hereagain, the surface can first be roughened over the entire area orlocally, in order to improve adhesion.

For gluing, the application of adhesive can take place over the entirearea or selectively—in the shape of the frame structure—onto the coverand/or the intermediate layer, or, in the case of a cover provided withthe frame structure, onto the wafer. Preferably, the adhesive is made ofthe same or a similar material as the frame structure. It is alsopossible to use a frame structure that is still sufficiently tacky forgluing, or to thermally soften the latter, or partially dissolve it, orotherwise make it tacky, for this purpose.

The adhesive can be applied in a layer thickness so that it achieves alayer height of 0.2 to 20 μm in the cured state. The application cantake place on one or also on both joining surfaces. If the cover isselected for this purpose, the application of adhesive can take place instructured manner, in accordance with the frame structure of the wafer,or also in simple manner, over the entire area.

Curing of the adhesive will preferably take place at temperatures thatare not too high, since otherwise, because of the mismatch between thethermal expansion coefficients of wafer and cover, as mentioned, whichcan hardly be avoided, displacements will occur (during heating) anddistortion will occur (during cooling). At a room temperature of 25° C.,for example, the curing temperature should therefore not exceed 50° C.

Therefore, a radiation-cured adhesive (VIS or UV) with openpre-activation (especially in the case of a non-transparent cover) orirradiation through the cover (if the latter is sufficiently permeablefor the wavelengths used) is particularly suitable. In each case, acold-curing adhesive can also be used, which is activated by means ofbeing mixed from its components.

If the aforementioned mismatch is sufficiently minimized, a heat-curingadhesive can also be used, of course. Then, however, it is advantageousto use the material of the wafer for the cover.

In an important case, however, a mismatch is desirable, specifically ifthe temperature coefficient of a specified characteristic (for examplethe center frequency of a SAW filter) is disadvantageously great becauseof the crystallographic wafer properties. According to the invention, apositive lock connection with a cover having suitable thermal expansionbehavior can be used in targeted manner, to reduce the expansioncoefficient of the component.

FIG. 7: In the next step, wedge-shaped cuts ES are produced in the backface of the wafer, along the separating lines TL. The cuts ES are madeso deep that they reach into the cover AD. The cuts divide theindividual structures of the frame structure in the center, withoutopening up the cavity that has been created for the component structuresBS.

The cuts ES can be produced by means of sawing, grinding, sandblasting,wet etching, dry etching, ultrasound erosion, or with a laser. They areproduced either with perpendicular walls having a depth to widthratio≦3, as walls inclined in V shape, with an opening angle up to 150°(preferably 30°-90°), or as U-shaped cuts. In order to create betterprerequisites for the subsequent metallization, a V-shaped sawed profileis preferred if the ratio of depth to width of the cuts exceeds a valueof approximately 1-2.

If an electrical connection of the back face metallization to aconductor of the wiring level is supposed to take place, in order toconnect the back face metallization with ground, for example, andthereby achieve electromagnetic shielding of the component, the cut musthave at least one cut edge with this conductor.

Before or after production of the cuts, it is possible to reduce thethickness of the wafer from the back. In this connection, it can beground down to a layer thickness of approximately 50 μm, or ablated insome other way. The firm connection with the frame structure and thecover assures sufficient mechanical stability in spite of the low layerthickness, so that the components are not damaged and their function isnot impaired.

In the next step, a back face metallization is applied to the back faceof the wafer W, which has been provided with the cuts ES, in a totalthickness of 10 to 20 μm, for example. Preferably, PVD or CVD methodsare used for this purpose, possibly in combination with galvanics. Themetallization can comprise a layer structure that contains Ti, W, V, Cr,Cu, Al, Ag, Sn, Pt, Pd, Au and/or Ni, or any desired layers or alloys ofthem, with a total thickness of 1-30 μm. In a preferred exemplaryembodiment, an adhesion layer is sputtered on, having a thickness≦2 μm(Ti, W, V, Ni and/or Cr), followed by an electrochemical thickening with5-30 μm Cu, for example. Subsequently, 0.05-5 μm Ag, Pd, Ni and/or Auare applied to the surface.

In a prior or subsequent step, the interfacial connections DK throughthe cover AD are produced.

For all the interfacial connections, it holds true that they arepreferably produced with a conical cross-section, wherein the greatercross-section of the conical opening faces outward, so that theproduction of a sealed and continuous metallization is facilitated.These holes can be drilled both before and after gluing, in the case ofall the method variants listed as examples. If this occurs afterwards,an end or a slow-down of the process can be advantageously achieved assoon as the break-through has occurred, in that wear rates of differentdegrees are used, or the work is performed with reproducible stops, orthe penetration into the next layer is reliably detected and theprocessing then stops.

The following methods can be used, for example:

The working depth can be controlled very accurately using an excimerlaser, by means of the number and the energy of the laser pulses. Sincedifferent materials have different ablating threshold intensities, anautomatic shutdown of the processing when a border surface has beenreached can also be achieved.

In the case of wet etching using a photoresist mask or withphoto-structured glass such as Foturan® as a cover, the selection of aselective etching agent, which essentially attacks only the glass, isadvantageous.

In the case of dry etching using a photoresist mask, control by way ofthe process time is possible. In addition, a selectively acting plasmaetching method can be selected.

In the case of drilling/grinding, the work can be carried out with depthmeasurement or a depth stop. Also, detection can take place using thechanged body sound when the border layer is reached.

In the case of sandblasting through a resist mask, brittle materialssuch as glass are worked away more quickly than elastic polymers.Therefore, in the case of this method, the process almost comes to astop at the border surface to the polymer (frame structure orintermediate layer).

In the case of ultrasound erosion with a sonotrode and abrasive materialsuspension, the same holds true as for sandblasting.

Subsequently, the holes for the interfacial connections are metallizedon their inside surfaces. For this purpose, a metallization is producedon the underside of the cover, over the entire area, for example using amethod analogous to the production of the back face metallization RM.Subsequently, the underside metallization is structured, so that anunderside contact UK is formed for every interfacial connection, by wayof which the component can subsequently be connected. For the sake ofsimplicity, only one interfacial connection is shown for everyindividual component.

Before or after structuring of the underside metallization, theinterfacial connections can be filled with bumps. For a particularlyefficient bump method, a solder mask (e.g., a dry resist film) isapplied and structured. The holes in the mask, above the contact bores,define the area of the subsequent under bump metallization (UBM). Theyare filled with solder paste by means of screen/template printing orgalvanically, or pre-finished solder beads are introduced. Aftermelting, the solder mask is removed and the exposed copper is etchedaway, the solder bump serving as an etch resist for the UBM.

In an embodiment according to the invention, the bump is formed in thata solid or hollow bead (diameter 30 to 300 μm) is partially pressed intothe metallized bore for the interfacial connection. Possible materialsfor the solid or hollow bead are glass, ceramic, metal, or polymers; thelatter are preferred because of their flexibility. In the case ofnon-conductive materials, the surface of the bead can be metallized. Toimprove the mechanical and electrical connection, a galvanic metalcoating that can be soldered subsequently takes place, which connectsthe exposed metallization collar of the bore of the interfacialconnection and the exposed sphere segment in gas-tight manner.

For other bump methods, which have already been proposed in greatnumbers, direct photo-technical structuring of the undersidemetallization, which particularly comprises copper, takes place. Nowsolder beads can again be inserted into the holes and melted, forexample.

FIG. 9 shows the possibility of providing different interfacialconnections, using a schematic cross-section through a sandwich-likestructure. The interfacial connection DK1 shown in the left in thefigure connects an underside contact UK1 with the surface of the waferW. An intermediate layer ZS is disposed between frame structure RS andcover AD, so that a cavity is formed between wafer and intermediatelayer ZS, in which the component structures (not shown in the drawing)are disposed in contact-free manner, without contact with theintermediate layer. On the surface of the intermediate layer (betweencover and intermediate layer), another wiring level VE is disposed,which is connected with the surface of the wafer, i.e., with a connectormetallization present there, by way of an interfacial connection DK2.

Another interfacial connection DK3 connects the underside contact UK3with the wiring level VE. As is already evident from the figure,additional area is created in the component, with the additional wiringlevel. In addition, the interfacial connection DK2, in particular, canbe positioned more precisely and adjusted relative to the componentstructures, i.e., their contact metallizations. For the interfacialconnection DK3, it holds true that its positioning can now take placewith greater tolerance, wherein the interfacial connection DK3 can alsobe implemented with a larger opening, without thereby increasing thearea required for the component.

Another possibility for producing the additional wiring level consistsof disposing it on the top of the cover, particularly opposite thecomponent structures within the cavity. In this case, an interfacialconnection still has to be made, in order to produce a contact betweenthe connector metallization on the surface of the wafer and the wiringlevel on the top of the cover. In order to produce the interfacialconnection, the method just described, using a protective varnish abovethe component structures, can be used.

Since it was possible to show the invention only on the basis of a fewexemplary embodiments, it is not limited to the precise configurationaccording to these embodiments and the related figures. Variations arepossible, particularly with regard to the spatial configuration of thecomponents, the number of intermediate layers and interfacialconnections, as well as the location of the interfacial connections. Theback face metallization can be partially removed from the back face ofthe wafer/chip. A cavity for the component structures is not absolutelynecessary. If the component structures are sufficiently non-sensitive,it is also possible that the cover or the intermediate layer restsdirectly on the front face of the chip/wafer. This is particularly truefor purely microelectronic components.

1. A component comprising: a chip having a first chip face and a secondchip face, the first chip face comprising component structures andconnector metallizations associated with the component structures; aframe structure on the first chip face and adjacent to the componentstructures; a cover over the frame structure, the cover having a firstcover face and a second cover face, the first cover face being closer tothe chip than the second cover face; a back metallization that is on thesecond chip face, on sides of the frame structure, and on sides of thecover; a contact on the second cover face; and a connection through thecover, the connection electrically connecting the component structuresand the contact; wherein the connection is metallized and sealed.
 2. Thecomponent of claim 1, wherein the chip and the cover define a cavitythat contains the component structures.
 3. The component of claim 1,wherein the frame structure comprises one or more interior structuresthat define one or more enclosures within the frame structure, the oneor more enclosures exposing the connector metallizations.
 4. Thecomponent of claim 1, further comprising wiring adjacent to the firstcover face, the wiring being connected to the connector metallizationsand to the connection.
 5. The component of claim 1, further comprising,between the cover and the frame structure: at least one intermediatelayer; and wiring adjacent to the first cover face.
 6. The component ofone of claims 4 or 5, wherein the wiring comprises metal structurescomprising at least one of conductors and passive components, thepassive components comprising at least one of capacitors, inductors, andresistors.
 7. The component of claim 1, wherein the cover comprises oneof ceramic, metal, and glass; and wherein the frame structure comprisesone of benzocyclobutene, polyimide, and benzoxazol.
 8. The component ofclaim 1, wherein the component is at least one of a microelectroniccomponent, a surface wave component, an FBAR resonator, a micro-opticcomponent, a micromechanical component, and a hybrid component.
 9. Thecomponent of claim 2, wherein the cavity contains a protective gashaving a spark-over resistance that is different from a spark-overresistance of air.
 10. The component of claim 1, wherein the connectionis conical in shape.
 11. A method of producing encapsulated components,comprising: adding component structures to a first face of a wafer;applying a frame structure to the first face of the wafer, the framestructure surrounding the component structures; adhering a cover to theframe structure thereby forming a cavity between the cover and thewafer, the component structures being inside the cavity, wherein thecover comprises a first cover face and a second cover face, the secondcover face being nearer to the wafer than the first cover face, thefirst cover face comprising a contact, and wherein the cover comprises aconnection that electrically connects the component structures to thecontact, the connection being sealed with a diffusion-proof undersidemetallization; forming cuts in a second face of the wafer that does notinclude the component structures, the cuts passing through the framestructure and into the cover, wherein the second face of the wafercomprises metallization; and separating the wafer into individualcomponents along the cuts.
 12. The method of claim 11, furthercomprising: applying an intermediate layer, the intermediate layer beingbetween the frame structure and the cover; and adding wiring to theintermediate layer, the wiring being connected to a metallization on thewafer via the connection.
 13. The method of claim 12, wherein theintermediate layer comprises a cover film that is glued to the framestructure.
 14. The method of claim 13, wherein applying the intermediatelayer comprises: applying the cover film and an ancillary film to theframe structure; structuring the cover film; and removing the ancillaryfilm.
 15. The method of claim 14, wherein the cover film is applied tothe ancillary film as a reaction resin in viscous form, and whereinstructuring comprising laminating and curing.
 16. The method of claim11, wherein applying the frame structure comprises shaping the framestructure.
 17. The method of claim 12, wherein the frame structureand/or the intermediate layer are applied via photo-structuring, etchingusing a resist mask, or laser ablation.
 18. The method of claim 11,further comprising: forming the metallization and the diffusion-proofunderside metallization by sputtering; and reinforcing the metallizationand the diffusion-proof underside metallization via wet chemistry orgalvanization.
 19. The method of claim 18, wherein the metallization isformed over an entire area of the second surface of the wafer; andwherein forming the metallization and/or the diffusion-proof undersidemetallization comprises structuring the metallization and/or thediffusion-proof underside metallization.
 20. The method of claim 12,further comprising: applying a protective coating to the componentstructures before the wiring is added; and removing the protectivecoating after the wiring is added.
 21. The method of claim 11, furthercomprising: roughening a surface of the wafer at a contact point withthe frame structure prior to applying the frame structure.
 22. Themethod of claim 12, wherein applying the intermediate layer comprisesshaping the intermediate layer.